Pipelined analog-to-digital converters (ADCs) represent one popular ADC architecture. FIG. 1 depicts an embodiment of a typical pipelined ADC 20, configured to convert an analog input signal AIN to a digital output signal DOUT, that includes a plurality of pipeline stages 24, each stage 24 receiving an individual analog input signal AI and generating an individual digital output signal DO, an analog output signal AO, an analog residue signal AR, and an amplified analog residue signal AAR, which is converted to a corresponding digitized residue DR. Each stage can include an ADC subcircuit 28 to generate the digital output DO, a digital-to-analog converter (DAC) 32 to generate the analog output AO, and a summation circuit 36 and amplifier circuit 40 to generate the analog residue AR and amplified analog residue AAR. The digital output DO of each stage 24 represents a digitalization, at a predetermined bit width, of the analog input AI received by that stage 24. The analog output AO represents a conversion of the digital output DO of that stage 24 back into analog form. The analog residue AR is a subtraction of the analog output AO from the analog input AI of that state 24, and represents the unconverted remainder of the analog input AI received by the stage 24. The digitized residue DR returned to a given stage 24 represents a digitalization of the analog residue AR by succeeding stages 24.
In operation, the pipelined ADC 20 converts the overall analog input AIN delivered to the first stage 24 by successively approximating in turn the analog input AI at each stage 24, to the predetermined bit width of that stage 24, then generating and amplifying the analog residue AR representing the unconverted remainder of the analog input AI at that stage 24, and passing the amplified residue MR to the next stage 24 and repeating the process. Ultimately, the ADC 20 can convert the original analog input AIN by combining the digital output DO produced by each of the individual stages 24, which can be performed by a delay and combine circuit 44, to successively build corresponding digitized residues DR into the overall digital output DOUT. In embodiments, overlap of the digital output DO between individual pipeline stages 24 can be used to improve accuracy of the overall pipelined ADC 20.
Problems exist, however, with the pipelined ADC architecture 20 depicted in FIG. 1. Inaccuracies in the generation of the amplified analog residue MR can limit the accuracy with which the ADC 20 as a whole operates, as later pipeline stages 24 will thereby convert an inaccurate remainder. This can manifest in reduced ADC performance parameters, such as SNR, linearity, etc. Two mechanisms that can reduce the accuracy of the generation of the amplified analog residue MR include a gain error in the amplifier 40 that amplifies the analog residue AR and component-value mismatches within the DAC 32 that generates the analog output AO from the digital output DO. First, in regard to gain error, the amplifier circuit 40 amplifies the analog residue AR by a predetermined gain to utilize more of the full scale of the input of succeeding pipeline stages 24. However, an error in the predetermined gain of the amplifier circuit 40 sends an erroneous amplified residue AAR to succeeding pipeline stages 24. Second, in regard to DAC mismatch error, the DAC 32 generates the analog output AO from the digital output DO, and the analog output AO is in turn used to generate the analog residue AR. However, many DACs 32 utilize capacitor or resistor arrays, or other component arrangements, the constituent components of which having predetermined component-value relationships, and deviation from these predetermined value relationships, as can result from manufacturing inaccuracies, can reduce the accuracy with which the analog output AO, and ultimately the analog residue AR, is produced.
Large capacitors and high power amplifiers have sometimes been used to mitigate these problems. However, these approaches can undesirably consume chip area and power, and may not even fix all of the above errors. Therefore, a need exists for a pipelined ADC architecture having a mechanism to correct for errors such as residue amplifier gain errors and DAC component-value mismatch errors, while not unnecessarily introducing space-consuming or overly complicated or power consuming circuitry.